For processing systems, designs of systems on chip (SoCs) involve routing between various system components integrated on a semiconductor chip. Wire routing congestion tends to be a challenge in designing networks-on-chip (NoCs) for the various routing requirements of the SoCs. Long wires and buses are particularly difficult for routing and may be prone to errors and data loss. Further, the use of dedicated wires for data communication between two entities may lead to inefficiencies. For example, while some wires may be over-utilized, there may be some wires which are under-utilized. Further, different packet formats in which data may be packaged may require different types of wires and transmission protocols. Sharing data traffic across wires in an effort to promote uniform utilization may lead to conflicts between various types or formats of data communicated among the various wires of a NoC.
Accordingly, a need exists for reducing the number of wires, as well as, improving the efficiency of utilization of existing wires of a network-on-chip (NoC).